As semiconductor manufacture advances to ultra large scale integration (ULSI), semiconductor devices continue to shrink in size. Circuit densities of several million transistors per die are now possible. As semiconductor devices shrink so does the die size. This has necessitated a reduction in bond pad sizes as well. It is anticipated that bond pads will soon be as small as 25 .mu.m.times.25 .mu.m on a side and spaced apart by only about 25 .mu.m. A thickness of the bond pad stack also continues to shrink so that bond pads as thin as 5000 .ANG. to 1 .mu.m are anticipated.
One problem with the shrinking dice and bond pads is that establishing an electrical connection to the bond pads is becoming more difficult. A preferred method of forming this electrical connection is by wire bonding. During a typical die packaging process, the bond pads formed on the face of the die are connected to a lead frame using fine bond wires. Typically, several dice are wire bonded to a single lead frame. The semiconductor dice are then encapsulated and a trim and form operation is used to separate the packaged dice and to bend the lead frame to form external leads in a desired configuration (e.g., J-bend, gull wing).
Apparatus for wire bonding semiconductor dice are well known in the art. Earlier versions of wire bonding apparatus were manually operated by an operator viewing the dice and bond pads through a microscope. More recently, automated wire bonding apparatus include vision systems for automatically sensing the locations of the bond pads on the dice and lead fingers of the leadframe to perform the wire bonding process. However, this technology is limited by the size and spacing of the bond pads which must be individually aligned and contacted by a wire bonding tool.
Another problem with current packaging technology is in the fixed relationship of the bond pads and interconnect circuitry on the die. For example, a conventional semiconductor DRAM die includes a memory cell array containing rows and columns of FETs associated with capacitors which store an electrical charge. The DRAM die also contains control and logic circuitry that interconnect to the memory cell array and terminate in the bond pads on the face of the die. The control and logic circuitry, which is typically on the periphery of the memory cell arrays, includes devices for addressing the array and for inputing and outputing data from the array. Typically the die is designed and constructed as a unitary structure containing both the memory cell array and the interconnect circuitry. The location of these components is fixed by the design and construction of the die.
In some applications it would be advantageous to be able to construct a die or a package in separate modules. For example, a memory cell array could be constructed as a component that is separate from the interconnect circuitry. This would allow a standard memory array to be provided but customized with different interconnect circuitry and bond pad arrangements for a particular application. Manufacturing costs could be reduced by the standardization and interchangeability of the different components. In addition, although contacts to the memory cells could remain small, the location and size of bond pads for connection to the outside could be made larger. This same scheme could be used to form a packaged die, to form an electrical connection to a die having microscopic bond pads, and to stack and interconnect dice contained on the wafers.
The present invention is directed to a method for forming an interconnect for semiconductor devices. The method can be used to form an electrical connection to microscopic contacts to semiconductor devices. In addition, the method can be used to form an electrical connection to microscopic bond pads for packaging a single die or multiple dice contained on a wafer.
Accordingly, it is an object of the present invention to provide an improved method for forming an interconnect for semiconductor devices.
It is a further object of the present invention to provide an improved semiconductor die having a separate interconnect substrate for making an electrical connection to memory devices contained in the die and for providing convenient sized and located bonds pads for connection to the outside.
It is a still further object of the present invention to provide an improved interconnect for making an electrical connection to microscopic bond pads on a semiconductor die.
It is yet another object of the present invention to provide an improved method for interconnecting multiple dice contained on a wafer and for interconnecting multiple wafers to one another.
Other objects, advantages and capabilities of the present invention will become more apparent as the description proceeds.